Development of Approximate Compressor Based Hybrid Dadda Multiplier for Image De-noising Applications

This paper proposes an approximate circuit design for 4:2 compressor which shows a significant amount of improvement in performance metrics (area, power consumption, delay, transistor count and error metrics) concerning the conventional 4:2 compressor. Subsequently, this paper also presents the hybrid architecture for the Dadda multiplier design, which enhances the efficiency of the system. This hybrid Dadda multiplier architecture is utilized in a modified median filter for image de-noising application. With the help of this technique, a significant amount of improvement is observed in the peak signal to noise ratio (PSNR) of the system. For circuit and system-level simulation is done in Cadence Virtuoso using gpdk 45nm library and MATLAB, respectively.