Case Study: SoC Performance Verification and Static Verification of RTL Parameters

Modern SoCs are developed by integrating several hundreds of IPs like hardware accelerators, I/O interfaces, memories, controllers, third party IPs, etc. It mostly uses several interconnects or cache coherent network for integration. Such complicated SoCs are prone to design errors that may affect, not only functionality but also performance. Performance bugs are much more difficult to detect in comparison to functional bugs. Even bug free performance will vary for a given application for a given SoC micro architecture and RTL design parameters. In majority of cases, performance bug detection and localization have been conducted manually and these are very challenging tasks. To localize such performance bugs in micro-architecture of various design components or interconnects using emulator/FPGA based environment is very challenging task. In this paper, we are discussing three approaches to deal with such problems. One approach deals with detection of critical data paths of the design by drawing directed graph of data paths. Later, dynamic performance simulations are run on those paths of the design by stressing all relevant design units. The second approach is about localization of performance bug. Third approach is to extract the RTL design parameters of the various components and analyze these parameters with various stakeholders before declaring the logic freeze of the device. On applying these, we found some critical performance bugs in design which were not found with conventional techniques. The proposed methodologies reduced overall performance verification time and improved quality of design.