Yield Impacting Defects and Prevention of Microbump Formation

Microbumping is one of key technologies for enabling 3D integration of semiconductor devices. Microbump based interconnect joining allows silicon dies with through-silicon vias (TSVs) to be stacked on each other [1]. Along with high level of integration, bumping process becomes more and more challenging. In this paper, some yield impacting defects during microbump fabrication are detected, root causes of these defects are discussed and analyzed. Prevention methods for these defects were proposed and demonstrated. With these defect prevention methods, yield can be enhanced without substantial increase in processing cost.