Radiation Hardened by Design Subsampling Phase-Locked Loop Techniques in PD-SOI

This article presents the radiation hardened by design (RHBD) techniques applied to a 15-GHz quadrature subsampling phase-locked loop (PLL) at a sub-50 nm partially depleted silicon-on-insulator technology node. Radiation-hardening techniques are integrated into a subsampling architecture for robust noise and radiation performance. Experimentally validated bias-dependent single-event models are used to characterize the radiation response, and the applicability of existing RHBD techniques to subsampling PLLs is examined. A significant vulnerability introduced in dual-loop architectures such as subsampling is identified and mitigated with a proposed technique. Favorable noise and loop perturbation suppression characteristics of the subsampling architecture are leveraged to develop a high-performance RHBD PLL, maintaining performance specifications comparable to unhardened designs.