FPGA Floating Point Fractional-Order Chaotic Map Image Encryption

Chaotic Logistic maps are iterative functions that are highly sensitive to initial conditions. They can be used for pseudorandom number key generation (PRNG) in encryption systems. Generalizing the conventional logistic map to the fractional-order domain adds extra degrees of freedom in designing larger key spaces enhancing the encryption security levels. The hardware implementation of the fractional-order map is a challenging task to achieve high accuracy and precision. For this reason, IEEE 754 Floating Point representation is employed in this paper to introduce the generalized fractional-order logistic map implementation on Virtex 5 FPGA achieving clock frequency of 260.4 MHz. The integration of the designed PRNG block in an image encryption system is also presented.