Generation of Efficient Self-adaptive Hardware Polar Decoders Using High-Level Synthesis

Recent advances in 5G digital communication standard implementations advocate for the use of polar codes for the Enhanced Mobile Broad Band (EMBB) control channels. However, in many cases, implementing efficient hardware decoder over a short duration is very challenging. Specialized knowledge is required to facilitate testing, rapid design iterations and fast prototyping. In this paper, we present a model-based design methodology to generate efficient hardware SC polar decoders from high-level synthesis tools. The abstraction level flexibility is evaluated and generated decoders architectures are compared to competing approaches. It is shown that the fine-tuning of computation parallelism, bit width, pruning level and working frequency enable high throughput decoder designs with moderate hardware complexities. Decoding throughput between 10 to 310 Mbit/s and hardware complexity between 1,000 and 21,000 LUTs are reported for the generated architectures.