Hardware Co-Simulation of LTE Turbo Code With Chaotic Interleaver And Improved Log-MAP Algorithm Using System Generator

An efficient LTE turbo code implement using Log-Maximum a Posteriori (MAP) Algorithm with reducing number of required cycles approximate by 50%. Turbo code design with different types of chaotic interleaver and implementation simplest type of chaotic interleaver (logistic map). The algorithm turbo decoder Log map has been used with an its improvement based on polynomial regression function to reduce the implementation complexity with 40 bit block size of the input. This paper present design and implementation of LTE turbo code using Xilinx System Generator linking between ISE 14.7 and Matlab 2013b, the design can achieve to apply on FPGA Kintex-7 and beneficial for real time application.