A Low-power H.265/HEVC 4K@30 Video Decoder with Dynamic Power Gating

This paper describes the design of a low-power H.265/HEVC 4096×2160@30fps decoder with dynamic power gating. We show that as the shrinking of technology node and the increasing of leakage power, circuit operating under “just-enough” or baseline frequency may not be the best solution in terms of total power consumption. By introducing various operating modes and dynamic power gating of inactive part of the design, we evaluate the total power consumptions of a H.265/HEVC video decoding system under different frequencies for various resolutions. We proposed both theoretical calculation and post-layout simulation result under 65nm technology, showing that the optimum power point occurs at a higher frequency other than minimum. By choosing proper operating mode, we are able to achieve up to 38% power reduction with negligible hardware overhead and no performance degradation.