Efficient VLSI Architectures of LILLIPUT Block Cipher for Resource-constrained RFID Devices

Information security in resource-constrained devices has attracted a great number of researchers in recent years. Secure communication suffers from resource limitation. Therefore, it is difficult to choose the most satisfactory security primitive for a particular application. LILLIPUT has been popular lightweight block cipher used to overcome such issues. In this paper, different architectures of LILLIPUT block cipher are presented. One of these designs enhances the efficiency in terms of throughput at the expense of a larger area. This design transforms the data input with the speed of 1132.40 Mbps for Field-Programmable Gate Arrays (FPGAs) of xc5vlx50t-3ff1136 device. In addition, the second implementation shares several building blocks for each round. Due to this, a compact structure is achieved by using the same reprogrammable device. Therefore, this proposed design results ina good area-time product. The proposed compact structure is most appropriate for low cost active smart devices. All results are simulated and verified for various families of XilinxISE design suite.