Time Efficient Design and FPGA Implementation of Distributed Canny Edge Detector Algorithm

Edge detection is one of the basic operations carried out in image processing and object identification. As it plays an important role in image processing which needs to be optimized, accurate and less latency architecture. This paper focuses on Edge detection using Adaptive threshold technique. The efficient Canny edge detector has been used in real time application. In this paper, the Gaussian filter is applied as preprocessing block to remove the high frequency edges. The Canny coefficients are approximated to suite the hardware requirements with less LUT's and further the adaptive threshold technique is applied to obtain the finer details of edges. The proposed method of edge computation using adaptive threshold reduces memory elements significantly, because it occupies less area, reduction in delay and increased efficiency without effecting detection performance. The proposed edge detection architecture is implemented using Xilinx system generator tool on Spartan6 ATLYS (XC6SLX45) board. It is observed that the proposed method is better in terms of time performance as compared to existing architectures.