FPGA Implementation of Power Efficient Approximate Multipliers

Approximate computing is a positive approach for energy efficient design of digital systems. This is an attractive archetype for approximation in multipliers that deals for a new design approach. For error resilient application, there is an increase in performance and power efficiency. This type of computing is particularly interested for computer arithmetic design. The multipliers are designed by introducing various probability terms and partial products. The design complexity is decreased with this type of multiplier. This work deals with the analysis and design of 4-bit and 8-bit exact and approximate multipliers. 4-2 compressors are used to modify the architecture and utilized in the proposed multiplier. This methodology was synthesized using Xilinx ISE. The hardware implementation is carried on ZYBO Zynq-7000 development board. The total power reduction for the approximate multiplier is 8% for 4-bit and 17.3% for 8-bit. This is much more efficient than exact multiplier design. The designed multiplier was tested on a 3 layer artificial neural network (ANN) model and reduction in power was obtained.