Multi-Bit Digital Receiver Design For Radar Signature Estimation

This paper brings out a unique FPGA based pulse detection and characterization approach for digital wideband ESM receiver targeted for EW applications. The proposed approach uses a high speed ADC and FPGA based architecture for sampling and digital signal processing of the received RADAR signals to extract the key parameters such as Frequency (F), Time of Arrival (TOA), Pulse Width (PW) and Pulse Repetition Interval (PRI). The proposed novel FFT based digital EW receiver is designed and verified by MATLAB and SIMULINK tools and VHDL code for same algorithm is generated using HDL Coder for FPGA implementation. The current paper uses 512-point FFT based digital EW receiver, requires minimum pulse width of 750 ns and frequency separation between two simultaneous pulses is 2.63 MHz to extract the key parameters accurately. The simulated and measured results for Pulse detection algorithm are presented.