FPGA Based Efficient Feed forward FFT Architecture

Feed forward FFT architectures provide an efficient method to compute FFT with a better hardware utilization, by making use of parallelism and pipelining concepts. Multipliers form an integral part of FFT architectures. Right choice of multiplier leads to improved area and speed. In this paper, we present a study on rotator allocation based Radix-2 feed forward FFT architectures with two different multipliers introduced into the architecture individually. The two architectures are designed considering 16 sample points with 4 inputs arriving at a time in parallel. The comparison of the architectures shows that the architecture with multiplier based on Modified Booth algorithm is more area efficient and has an improvement in speed. The synthesis is done on Virtex-6 FPGA, XC6VSX475T-l FF1156.