Fast Physical Verification for 16nm Package Electrical Performance

As the silicon technology shrinking transistors to deep nanometer, the IO speed and logic density drive up the package design complexity drastically. The design performance validation is no longer scalable by resorting to traditional electrical modeling owing to the computation speed and memory gated by fine line geometry, layer count and increasingly higher bandwidth. While the electrical modeling remains to be the choice for selected critical nets, the full physical design verification becomes impractical electrically. On the other hand, system users demand all I/O and all powers to meet the same stringent specifications. We hereby report a fast, effective, large-scale verification method by cross-correlating physical parameter and shape compliance to the electrical design rule and template respectively. The method can further extract electrical parameters such as spreading inductance of a power distribution network (PDN) with using the concept of square inductance. The approach is implemented in the Xilinx's 16nm 10GS/s RFSoC FPGA product package design.