Flexible Processor Architecture Design

This paper provides an alternative approach to the modern processor architecture design using a Transport Triggered Architecture (TTA). The aim has been focused on flexible computer architecture design, that can allow execution of multiple Instruction Sets (Hardware) or Byte Codes (Virtual Machines) to emulate other Instruction Set Architectures (ISAs). The idea is to design a vertical microcoded processor, that can enable basic register to register data transfer from one address to another using TTA system. This results in execution of complex instructions in a multi-cycle fashion. The target then boils down to convert any currently known instructions to just a mere multiple register to register word transfers that would in-turn invoke other combinational or sequential hardware modules to execute the instruction.