Design And Analysis of 4-Bit Adder Using Delay-Insensitive Ternary Logic For Secure Hardware

This paper presents an asynchronous design methodology, Delay-Insensitive Ternary Logic (DITL). The DITL has three voltage levels, Vdd, ½ Vdd, and Gnd, to predetermine on a single wire the three different states of delay-insensitive logics are DATA0, DATA1, and NULL. The proposed research work is to design a DITL 4-bit adder at the transistor level using DITL based on the concept of null convention logic (NCL) and pre-charge half buffer (PCHB to mitigate side-channel attacks, and to validate the efficiency of DITL various performance parameters viz. propagation delay, total area, and power dissipation are measured to defend against side-channel attacks. The proposed DITL 4-bit adder at 90nm CMOS technology node with a supply voltage of 1.1V exhibits an average power dissipation of 128.3 μW and propagation delay of 258.9 ns. As compared to NCL-10G the delay and power dissipation of the DITL 4-bit adder is reduced by 24% and 55%, respectively. Thus, timing and power factors of DITL 4-bit adder shows the least variation than NCL-10G. Therefore, the proposed DITL-4bit adder is resistant to power and timing attacks.