High-speed, high-reliability circuit design for megabit DRAM

Circuit techniques for improving the speed and reliability of submicrometer geometry CMOS DRAMs are described. Double-bootstrap voltages are eliminated with an internal voltage supply and a unique word-line driver, reducing stress on short-channel devices. A row and column redundancy technique equivalent to physical disconnect of word lines and bit lines solves leakage problems. Speed enhancements are achieved through bit-line isolation for accelerated column access, a high-speed SRAM-style data path, and by tailoring sensing currents within the limitations of package inductance. The design of a fast 1-Mb DRAM employing these circuits is outlined.<
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