Ultra-Thin Si(1_x) Ge(x) Envelope Layer Induced Hole Quantum Well in Cylindrical Surrounding Gate p-FET with ITRS Considerations

In this paper, a 3-Dimensional Silicon-Germanium (SiGe) enveloped Cylindrical Nanowire Field-Effect Transistor is proposed with International technology roadmap of semiconductors (ITRS) consideration. This work emphasizes on the scaling of gate length, drive current, transition frequency and gain with the variation of mole fraction of Ge for low power application. To overcome the trapped interface state charge and gate leakage current, a high-K metal gate oxide HfO
₂
has been employed. The simulated device shows the saturation current 80μA/μm as per the 2021-ITRS constraint. The low subthreshold swing of 60 mv/dec (near the thermal limit), and high I
_ON
/I
_OFF
ratio of 1010 at 20 nm gate length suggests the suitability of the device for digital applications. Scaling down gate length 20 nm to 5 nm reduces the overall gain from 24.5 dB to 6.21 dB which can be attributed to the reduction in channel resistance.