An In-Memory Architecture for Machine Learning Classifier Using Logistic Regression

The paper proposes a 8T SRAM array which performs machine-learning classification using logistic regression. A prototype 128 x 128 SRAM array, implemented in a 65-nm CMOS process, demonstrates ten-way classification to recognize the MNIST hand-written digits. In this proposed architecture, the SRAM array stores the binary image which is obtained by down-sampling the 28 x 28 test image to 10 x 10. The down-sampled image is converted to binary image which requires less memory space compared to the original image and has minimum required information needed for image classification. The training weights are applied to the digital-toanalog converter (DAC) and the analog output voltage of the DAC is supplied to the classify wordline of the memory array. The classify bitline voltage of each column represents sum of product of weight vector and input feature vector (binary image). The proposed architecture is validated on MNIST handwritten digits (10k test images) and it operates almost at the same frequency in both SRAM and classify mode with very less area overhead.