Area-Efficient Parallel-Prefix Binary Comparator

Binary comparator is the most basic component for comparing the two binary operands in different arithmetic functional blocks, digital communication and encryption/ decryption devices. Normally, the binary comparator gives three decision outputs in many cases but in some applications like coupled linear congruential generator (CLCG) based pseudorandom bit generator (PRBG), it gives single output decision on the basis of inequality equation x
_i
> y
_i
. Magnitude and mux-based comparator are the most commonly used binary comparator for comparing the two binary operands. However, the parallel prefix structure of these comparators increases the area in the order of O(n). Therefore, in this paper a new area efficient single decision output binary comparator is developed using merging circuit technique for the computation of inequality comparison x
_i
> y
_i
in CLCG based PRBG methods. The use of merging circuit in the prefix computation stages considerably reduces the area of the proposed binary comparator as compared to other popular exiting comparator architectures. The proposed comparator of 32- and 64- bit word size is designed with Verilog HDL and implemented on Spartan3E FPGA device to study its hardware performances. It reports that the proposed 32- bit comparator consumes 23.6% and 16.1% less LUT area as compared to the magnitude and mux-based comparators respectively.