Design of Efficient 2–4 Modified Mixed Logic Design Decoder

This paper proposes a Modified-Mixed Logic Design (MMLD) for the decoders, which comprises full swing Gate diffusion input (GDI) technique, conventional complementary metal oxide semiconductor (CMOS) and Dual value logic (DVL). Two modernized topologies: 14T and 15T decoders are designed for minimizing power dissipation and propagation delay respectively. Each traditional and inverting decoder is enforced in every case. Compared to the conventional CMOS logic, the proposed decoder gives full swing with reduced count of the transistors. The spread of Cadence (Virtuoso) simulation at 45nm is used for implementing this proposed mixed logic decoder at different frequencies with different various supply voltages, which shows reduction in power dissipation & propagation delay as compared to typical CMOS and existing mixed logic design.