Design and Verification of Analog Integrated Circuits Using Free or Open source EDA Tools

In this paper, a design methodology for carrying out all the steps involved in a typical analog design flow, using free or open source electronic design automation [EDA] tools is proposed. Implementation of a three stage CMOS operational amplifier is chosen for demonstration. gEDA-gschem tool is utilized for schematic capture and SPICE net list generation. Electric-VLSI is a state of the art EDA tool which is used for laying out the op-amp, design rule checking [DRC], verifying layout versus schematic [LVS] and generating parasitic extracted SPICE net list. The SPICE net list are simulated with the help of versatile, electronics and electric circuit simulator, Ngspice. The scripting language provided by Ngspice is used for performing corner analysis and Monte-Carlo simulations. Simulation results reveal that the designed operational amplifier meets the desired specifications. Corner and Monte-Carlo analysis show that the op-amp is robust against process variations and mismatch.