Design of Low Power and High Speed VLSI Domino Logic Circuit

The power dissipation of the circuit is reduced in normal mode of operation compared to test mode for any low power VLSI designs. This intern reduces the battery life of the device. Therefore, reducing power dissipation during normal operation has become a critical objective in today’s any VLSI circuit designs. The power dissipation of the circuit can be reduced at different stages of the circuit by the designers. For any CMOS circuits, power dissipation may be dynamic or static. The dynamic power dissipation exists in CMOS circuit due to switching activates between the test patterns. But the static power dissipation due to leakage in the device and it can be neglected. The domino circuits are used in various circuits, especially in memory, multiplexor, comparator and arithmetic circuit and also used in full adders that are the most important part of a CPU. Additionally, the effective implementation of domino logic in arithmetic unit and floating point units plays important role in the application circuit like microprocessor and Digital signal processor. Various design approaches had been investigated for realizing domino CMOS. The Extensive use of high speed domino circuits attracts many researchers in this field. There are various issues related to domino circuits, such as power consumption, speed and noise immunity.