Design and Simulation of a Capless Low Drop Out Voltage Regulator

The changing requirements of the industry is directing towards the full integration of SoC. This requires the power management block to have the Low Drop Out(LDO) regulator with reduced external capacitor. This paper proposes the study of behavior of the LDO voltage regulator with an external capacitor and capless low drop out voltage regulator. The regulated voltage of 1.8V is obtained using the typical power supply of 2.2V. The total quiescent current used in the circuit is less than 30uA with the load current variation of 0 to 20mA. The capless LDO architecture is verified in the UMC 180nm technology. The architecture provides a stable regulated voltage of 1.8V with both line and load variations and also for the transient variations. The stability issues are overcome using the compensation techniques which uses a current amplifier and a capacitor in the differentiator configuration. The current amplifier implemented uses current mirror with current copying ratio of unity.