Characterization of Library Cells for Open-circuit Defect Exposure: A Systematic Methodology

Ensuring high defect coverage for advanced CMOS technology nodes has been a major challenge for the IC test industry. Traditional test methods using fault models such as stuck-at and transition faults with a primitive gate-level abstraction of design netlists have been shown to be inadequate for detecting open-circuit and short-circuit defects within instances of standard cells used in those netlists. Recent advances in Cell-Aware Test (CAT) using single pattern and two pattern tests have demonstrated increased coverage of such defects in industrial IC designs. However, the simulation overhead of defect characterization for all the cells in a library practically limits the size of defects that are explored to large magnitudes. Furthermore, certain effects such as charge sharing within cells can necessitate tests that span more than two time frames to expose subtle defects. This work, through simulation, identifies defects of certain sizes that can go undetected by current methods. It then proposes an algorithmic approach towards cell characterization that can result in faster identification of cell input stimuli vis-a-vis a defect simulation based method.