Gate stress induced threshold voltage instability and its significance for reliable threshold voltage measurement in p-GaN HEMT

In this study we investigate the effect induced by standard transfer characteristic measurement (I
_D
-V
_G
) which is used to quantify threshold voltage (V
_th
), on threshold voltage (V
_th
) itself and a technique to mitigate this effect for a reliable V
_th
measurement is proposed for a p-GaN gate AIGaN/GaN-on-SiHEMT. Time-dependent drain current (I
_D
) sampling measurements at low gate stress voltages (close to the nominal V
_th
) reveal the existence of a small-time range during which I
_D
is stable (I
_Dstable
-T
_zone
), before and after which I
_D
marginally rises and substantially decays respectively. We find that both in the standard pulsed and DC step I
_D
-V
_G
measurements a change in pulse on-time (Ton) and step time (Tstep) respectively, can lead to a variation in the V
_th
measured of up to 20%. This change is ascribed to the fact that the choice of Ton and Tstep affect the bias history experienced by the gate during I
_D
-V
_G
. Further, we demonstrate that by choosing Ton, Tstep such that the Id measurement happens in the aforementioned I
_Dstable
-T
_zone
extracted from the I
_D
sampling measurements the gate is more stable and V
_th
measured is closer to the quoted nominal value.