Compiler-Based High-Level Synthesis of Application-Specific Processors on FPGAs

In order to meet tight performance and/or energy constraints of embedded systems, the implementation of applications in hardware is often a must. However, mapping of algorithms to platforms, as for example Field-Programmable Gate Arrays (FPGAs), still requires comprehensive hardware knowledge and sometimes long design cycles. Modern High-Level Synthesis (HLS) offers a means to ease the generation of hardware implementations from a software specification of an application. Although these tools have improved greatly in recent years, they often do not provide full coverage of important programming constructs and are therefore of limited use when used with existing or automatically generated code. Soft-core processors implemented with FPGA-logic can circumvent this limitation. However, these come with drawbacks in terms of performance and resource requirements as a general-purpose architecture is used to implement the application in software rather than as a highly specialized circuit. As a remedy, our work presents a novel compiler-based synthesis methodology that generates networks of Application-Specific Instruction Set Processors (ASIPs) from unmodified C/C++ algorithms. We thereby bridge the gap between traditional soft-core processors and HLS. To show the practicability of our approach, we present a case study of a JPEG decoder application while investigating design objectives like resource costs and performance. Apart from the generality of the compiler-based approach, our approach also shows better results in terms of required hardware resources and execution times compared to Instruction Set Architecture (ISA)-fixed commercial Xilinx MicroBlaze soft-cores.