Open Defect Detection Not Utilizing Boundary Scan Flip-Flops in Assembled Circuit Boards

An electrical interconnect test method is proposed to detect and locate open defects occurring at interconnects between integrated circuits (ICs) and a printed circuit board. The test method does not utilize boundary scan flip-flops. It is based on a quiescent supply current that is made to flow through an interconnect under test by embedding a test circuit into the ICs. The circuit consists of MOS switches for each input pin of the ICs and its switch control circuit. SPICE simulations are used to examine whether open defects at the interconnects can be detected using this method. The simulation results indicate that the following defective interconnects are detected in addition to defective ones modeled as an open-circuit fault at a test speed of 25 MHz: defective interconnects modeled as a resistor of 150 Ω generating an additional propagation delay of 482 ps and as a capacitor of 4 pF generating an additional propagation delay of 128 ps and no logical changes. Testability of open defects using this test method is also examined experimentally by prototyping an IC in which the test circuit is embedded. The experiments indicate that a resistive interconnect of 150 Ω and a defective one modeled as a capacitor of 2.2 nF can be detected by the test method at a test speed of 0.5 MHz.