Enabling Sub-5nm CMOS Technology Scaling Thinner and Taller!

Scaling beyond 5nm will bring us into the post FinFET era where new device architectures optimized for CMOS logic scaling will be required. In this paper, the evolution to vertically stacked Nanosheets, Forksheet, and finally CFET are reviewed in conjunction with buried power rails and wrap around contact. Performance and area impact of these architectures are evaluated both at standard cell as well as block level to provide realistic PPA estimate for true technology scaling.