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3D heterogeneous integration of high performance high-K metal gate GaN NMOS and Si PMOS transistors on 300mm high-resistivity Si substrate for energy-efficient and compact power delivery, RF (5G and beyond) and SoC applications | IEEE Conference Publication | IEEE Xplore

3D heterogeneous integration of high performance high-K metal gate GaN NMOS and Si PMOS transistors on 300mm high-resistivity Si substrate for energy-efficient and compact power delivery, RF (5G and beyond) and SoC applications


Abstract:

We have demonstrated industry’s first 300mm 3D heterogeneous integration of high performance, low-leakage high-K dielectric metal gate enhancement-mode (e-mode) GaN NMOS ...Show More

Abstract:

We have demonstrated industry’s first 300mm 3D heterogeneous integration of high performance, low-leakage high-K dielectric metal gate enhancement-mode (e-mode) GaN NMOS and Si PMOS transistors on 300mm high-resistivity (HR) Si(111) substrate, enabled by 300mm GaN MOCVD epitaxy and 300mm 3D layer transfer. The fabricated (bottom device layer) high-K dielectric e-mode GaN NMOS transistors, integrated on a 300mm HR Si(111) substrate, show excellent electrical characteristics and figure-of-merits (FOM) for realizing energy-efficient, compact voltage regulators and RF front-end components such as power amplifiers, low-noise amplifiers and RF switches, with (i) IOFF as low as 100pA/μm (VD=5V, VG=0V), (ii) high ID,max=1.5mA/μm; (iii) RON as low as 610Ω-μm, significantly better than industry-standard Si transistors at equivalent drain breakdown (BVD), (iv) excellent RF performance: fT=190GHz, fMAX=300GHz, PAE=56% at mmwave frequency (f=28GHz), and PAE=70% at sub-7GHz (f=5GHz), significantly better than industry-standard GaAs and Si RF transistors, (v) excellent RF switch FOM, RonCoff=110fs, and (vi) low noise figure, NFmin=1.36dB (f=28GHz), 0.4dB (f=5GHz) and 0.27dB (f=1.8GHz), all at SoC-compatible voltages. The fabricated (top device layer) LG=65nm and 130nm Si PMOS transistors, which are monolithically integrated on top of the bottom GaN NMOS transistors by 300mm 3D layer transfer, show respectively, high drive current of 0.85mA/μm, and low Ioff of 150pA/μm at VD=-1.2V. Such a monolithic 3D integration of GaN NMOS and Si PMOS enables full integration of energy-efficient, truly compact power delivery and RF solutions with CMOS digital signal processing, logic computation and control, memory functions and analog circuitries for next generation power delivery, RF (5G and beyond) and SoC applications.
Date of Conference: 07-11 December 2019
Date Added to IEEE Xplore: 13 February 2020
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Conference Location: San Francisco, CA, USA

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