First Demonstration of Vertical Ge0.92Sn0.08/Ge and Ge GAA Nanowire nMOSFETs with Low SS of 66 mV/dec and Small DIBL of 35 mV/V

We demonstrate for the first time, vertical Ge_0.92Sn_0.08/Ge and Ge gate-all-around (GAA) nanowire (NW) pMOSFETs fabricated with a CMOS compatible top-down approach. Vertical Ge NWs with 20 nm diameter and smooth sidewalls were achieved with optimized ICP-RIE and digital etching. Employing a GAA architecture, post-oxidation passivation and NiGe contacts, high performance Ge NW pFETs exhibit low SS of 66 mV/dec, small DIBL of 35 mV/V and a high I_ON/I_OFF ratio of 3×10⁶. Further performance improvements, like ION, DIBL were achieved by adopting GeSn as the source. At V_GS-V_TH = -0.5V, ~32% ION enhancement for vertical heterojunction Ge_0.92Sn_0.08/Ge NW pFET is obtained compared with Ge control device. This is attributed to a smaller NiGeSn/GeSn contact resistivity and the existence of a valence band offset ΔE_V at the Ge_0.92Sn_0.08/Ge heterojunction.