3D Scalable, Wake-up Free, and Highly Reliable FRAM Technology with Stress-Engineered HfZrOx

The major challenge of FRAM scaling is to maintain high polarization density on the vertical sidewall of 3D ferroelectric capacitors. We reported a CMOS-compatible HfZrO
x
FRAM technology that shows a wake-up free character, 10
¹⁰
/10
⁹
endurance cycles, extrapolated 10-year retention at 105°C/85°C, and initial P
r
= 25/18 μC/cm
²
for 2D/3D FRAM, respectively. The strain effect at atomic interfaces is considered by the density functional theory (DFT) simulation. Two simple yet effective methods, stress engineering and optimized interface orientation, are proposed to facilitate preferential transition from tetragonal to orthorhombic phase. The test chip of 2T2C 3D FRAM demonstrates a fast sensing speed of 17 MHz at V
DD
of 4V.