An Automated Place and Route Methodology for Asynchronous SFQ Circuit Design

The present work proposes an Automated Place and Route Methodology for asynchronous SFQ circuits using PTL lines and a commercial EDA tool, Cadence's Innovus. At the cell level, dual rail SFQ Asynchronous standard cells were developed for the MIT Lincoln Labs SFQ5ee Process to be implemented in the Place and Route methodology. Python Scripts were written that could convert single rail netlists, obtained through the synthesis tool Design Vision from Synopsys, into dual rail asynchronous cells. Automatic Place and Route of Verilog based designs using these standard cells produced layouts that passed checks for Layout vs Schematic (LVS) and Design Rule Check (DRC). Then, the transmission line lengths are back annotated from the placed and routed design into analog simulation to simulate propagation delay.