A Statistical Static Timing Analysis Tool for Superconducting Single-Flux-Quantum Circuits

As a beyond-CMOS technology, superconducting single-flux-quantum (SFQ) technology promises fast processing speed and excellent energy efficiency. With the increasing complexity of SFQ circuits, the accurate and fast estimation of the workable clock period under process variation becomes more urgent. However, the estimation of the minimum workable clock period is difficult due to the spatial correlation of physical parameters and the non-normal distribution of timing parameters (propagation delay, setup time, and hold time). Therefore, a good statistical timing analysis (SSTA) tool for SFQ circuits is necessary. This paper presents a bootstrap-based statistical static timing analysis tool called qSSTA. qSSTA can reasonably estimate a minimum workable clock period by executing a large amount of bootstrap iterations from the discrete sampling spaces of all gates under a certain correlation specification. By applying path pruning methods, qSSTA skips the calculations on unimportant paths and hence reduce run time and memory. Experimental results show that the size of important paths could be small. Among 19114 paths of the 16-bit integer divider, only 73 paths are important to estimate minimum workable clock period. We only need 84.21 seconds to run 10,000 iterations.