Circuit Reliability of Low-Power RRAM-Based Logic-in-Memory Architectures

Logic circuits based on Resistive RAM (RRAM) devices and the material implication logic (IMPLY) are promising solutions for low-power logic-in-memory (LiM) architectures. Still, their diffusion is limited by their high design complexity resulting from device and circuit non-idealities. These non-idealities are usually overlooked in the design phase when using simplified RRAM models, thus leading to unreliable designs. In this work, we derive correct design strategies for reliability of RRAM-based LiM circuits and quantitatively evaluate circuit performances using a physics-based compact model.