Performance Analysis of Adder Architecture using Modified Pass transistor Adiabatic Logic Circuits

This article analyses the prominence of modified pass transistor adiabatic logic circuits, such as IPAL and EEPAL. Both these logic circuits are operated by four phase trapezoidal power clock source and these employ optimal number of devices in it. Conventional MOSFET devices suffer from short channel effects the as device size scales down to lower technology nodes. FinFET acts as a promising device which can overcome the limitations of MOSFET. The FinFET based quasi-adiabatic logic circuits operating using four phase power clock supplies, namely, 2N2P, 2N2N2P, PFAL, EEPAL and IPAL structures have been considered for the analysis. All the circuits have been designed using FinFET 32nm technology in Cadence® Virtuoso EDA tool environment and the results authenticate the improved energy efficiency features of EEPAL and IPAL.