A comparative study on the performance of FPGA implementations of high-speed single-precision binary floating-point multipliers

Floating-point representation is flexible and extremely scalable compared to fixed-point representation due to its high dynamic range and accuracy in modeling fractional numbers, which are the prerequisites of many fields of computation such as signal and graphics processing, and astronomical and subatomic physics calculations. The IEEE 754 format defines the standard for single-precision (32-bit) floating-point numbers and splits a 32-bit number into three parts, namely the sign, exponent, and mantissa/significand. The multiplier design influences the overall performance, area, and latency of a floating-point multiplier. This paper studies the performance characteristics of three different floating-point multiplier schemes, namely binary array multiplier and scaled versions of Vedic multiplier and Wallace tree multiplier using a simple ripple-carry adder design for the addition of intermediate products resulting from mantissa multiplication. The designs coded in Verilog HDL are simulated using Xilinx ISim. RTL blocks are synthesized using Xilinx ISE 14.7 with implementations targeted on a Spartan6 XC6SLX45 FPGA device. The floating-point multipliers are analyzed and compared based on performance characteristics for efficiency, such as area, latency, static and dynamic power consumption, and power delay product. Notably, the designed Wallace tree multiplier exhibits a marked 31.13% latency reduction over the conventional array multiplier with a concomitant increase of 53.54% in the device area.