Increased Fault Isolation Efficiency by Using Scan Cell Visualizer for Scan Chain Failures

Scan design, being part of the most commonly practiced form of Design for Testability (DFT) has been developed to enable software based diagnosis for scan chain failures. Tessent Diagnosis helps to narrow down the reported failures to a suspected failing chain [1] - [5]. Unfortunately, scan chains can consist of hundreds to thousands of individual latches that can represent potential defect candidates and are typically distributed across the entire chip. Implementing global fault isolation techniques, which includes Photon Emission Microscopy (PEM) analysis, can lead to a collection of numerous anomalous emission spots. Cross mapping both the PEM results and the hundreds to thousands of individual scan cells to the CAD layout is both time-consuming and labor intensive. Moreover, selective cross mapping does not reveal the scan latches in chronological order, which is important for any scan chain analysis. One possible solution is to spatially map the scan latch list from the diagnosis file to the CAD layout to visualize the scan latch distribution quickly. This paper describes the use of this Scan Cell Visualizer through the use of case studies to demonstrate improved layout mapping efficiency and reduced overall failure analysis cycle time.