GPU-HBM SiP Interconnect Link Test and Repair

With the advent of HBM as a fast, high capacity, extremely-efficient CoWoS stacked memory architecture, its testing has presented lots of challenges. Due to the tiny geometry of the microbump interface and complex nature of the packaging process involved, with the GPU and HBM dies tightly coupled on the same Passive Silicon Interposer Package, the probability of introduction of defects increases greatly. These assembly defects usually manifest as open, short or resistive joints. Hence there is a need to test the SiP for link defects and repair them to restore the functionality of the SiP. This paper describes NVIDIA's comprehensive solution for Link Test and Repair, which helps achieve the industry-best high-volume ATE production screening program.