Applications of Test Techniques for Improving Silicon to Pre-Silicon Timing Correlation

Static Timing Analysis tools are used during design timing closure for 1) predicting the failing frequency of timing critical paths and 2) determining the relative order of criticality of the paths. However, there is often a mismatch in maximum frequency (Fmax) predicted by STA tool and Fmax observed in silicon even after removing the added worst-case margins. Moreover, the timing slack histogram of critical paths reported by STA tool is typically steep and can mismatch the actual failing path histogram in silicon which is more gradual. This mismatched path ordering results in wasted timing closure effort on paths which are not the frequency limiters. The device Fmax can be improved if real critical paths as observed in silicon can be determined during design. We describe two methodologies in this work that use traditional test patterns to identify the reasons for mismatch between silicon and STA tool data. 1) Path Delay patterns are used to correlate Fmax of paths. 2) Transition patterns are used to correlate the slack based ordering of paths. As part of this work, we also developed a timing methodology that complements traditional STA which will address this mismatch.