Vertical Ge Gate-All-Around Nanowire pMOSFETs With a Diameter Down to 20 nm

In this work, we demonstrate vertical Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a CMOS compatible top-down approach. Vertical Ge nanowires with diameters down to 20 nm and an aspect ratio of ~11 were achieved by optimized Cl
₂
-based dry etching and self-limiting digital etching. Employing a GAA architecture, post-oxidation passivation and NiGe contacts, high performance Ge nanowire pMOSFETs exhibit low SS of 66 mV/dec, small DIBL of 35 mV/V and a high I
_ON
/I
_OFF
ratio of 2.1 × 10
⁶
. The electrical behavior was also studied with temperature-dependent measurements. The deviation between the experimental SS and the ideal kT/q ·ln10 values stems from the density of interface traps (D
_it
). Our measurements suggest that lowering the top contact resistance is a key to further performance improvement of vertical Ge GAA nanowire transistors.