Improved Topology of Symmetrical Multilevel Inverter With Reduced Number of Switching Devices

In this paper, an improved topology of symmetrically operated multilevel inverter with reduced number of switches is proposed. A factor of merit about this topology is that it allows cascaded configuration to produce a higher number of output levels. Additionally, an appropriate technique for the required pulse width modulations (PWMs) on the switches is also described. The topology is compared with several classic and newer reduced switch multilevel inverters (MLI) in terms of the number of switches, DC sources, output levels and basic units. An in-depth study on the 9-level (9-L) operation of the proposed topology is presented where the voltage, current and power-sharing by each DC source are analysed. The power shared by the first DC source is found to be the highest, followed by the second, third and fourth DC sources. From the ideal simulation using Matlab Simulink environment, the proposed topology is capable to deliver power to the load at almost unity power ratio of above 99%, rendering it very much suitable for real time application. Furthermore, the study is extended to include the cascaded 17-level (17-L) operation of the proposed topology. It is noted that higher cascaded configuration of the proposed topology will allow higher number of output levels, resulting in lower total harmonic distortion (THD).