High-Performance Implementation of Dynamically Configurable Load Balancing Engine on FPGA

Load balancing technology plays an important role in task distribution. At present, mainstream solutions are implemented by software, and the delay introduced is longer; others implemented by hardware do not achieve excellent performance. This article proposes an implementation scheme of a reconfigurable load balancing engine on an FPGA. This engine could distribute network packets to CPU cores over a five-tuple, and the delay brought by balancing algorithm is only about 26 ns. Furthermore, this engine can process all frame sizes of packets at 100 percent line rate and zero packet loss rate, achieving excellent performance. At the same time, this engine supports dynamic configuration and can be set flexibly according to different scenarios.