Adjoint Optimization of Efficient CMOS-Compatible Si-SiN Vertical Grating Couplers for DWDM Applications

Data communication in silicon photonic interconnects requires efficient and broadband on/off-chip coupling components. Recently, perfectly vertically-emitting grating couplers have been proposed to increase spatial I/O density of the optical link and potentially improve manufacturing costs and ease of optical beam characterization. In this article, adjoint optimization was leveraged in the design of low-loss single (silicon) and dual layer (silicon + silicon nitride) perfectly-vertical grating couplers that are compatible with a scalable silicon-on-insulator (SOI) platform for the 65 nm CMOS technology node. In simulation, the best design peaks at -0.52 dB insertion loss with a 1 dB-bandwidth of 24 nm at the 1310 nm datacom wavelength.