FPGA-Based Optimized Convolutional Neural Network Framework for Handwritten Digit Recognition

The size of ConNN (Convolutional neural network) tends to increase every year. Thus, it consumes plenty of power to be able to run it. To reduce the power consumption, choosing the right hardware platform is important. Field programmable gate area (FPGA) is also known as low power platform for low level digital design. Therefore, this paper proposes an implementation of ConNN using FPGA in order to reduce the power consumption. We describe the simple ConNN which is optimized ConNN framework compatible with FPGA. Moreover, we implement the handwritten digit recognition to evaluate the performance of our framework.