A Compact Inductorless 32 GHz Divide-by-2 CML Frequency Divider on 22 nm FD-SOI Technology

This paper presents a compact divide-by-2 frequency divider based on CML D-flipflops suitable for operation in low-power (LP) or high-performance (HP) mode. In LP mode the divider locks in the 10 −28 GHz range, and in HP mode in the 12.5 −32 GHz range, corresponding to 119% and 118% relative locking ranges. The circuit has been manufactured on a 22 nm FD-SOI CMOS process and consumes 3.5 mW and 6 mW from a 0.8 V and a 1 V supply while generating a −21 dBm and −15 dBm output signal in low power and high performance modes, respectively. The divider does not use any peaking inductors, which allowed an active core area occupation of only $255\ \boldsymbol{\mu}\mathbf{m}^{2}$. The small area and the absence of bias inputs allows its seamless integration into frequency synthesizer or clock recovery circuits.