Low-power hardware implementation of SNN with decision block for recognition tasks

We present a fully configurable spiking convolutional node that can be used to ensemble large arbitrary Convolutional Neural Networks (ConvNets) on FPGA. The node includes a rate saturation mechanism to implement a refractory period. Using this node, a 4-layer ConvNet with 22 convolutional nodes and a decision block has been implemented in an FPGA. This network has been trained for recognition of poker card symbols and tested with a stimulus with 40 poker cards recorded by a silicon retina. In this paper, we study different strategies for the decision block to maximize the recognition rate with minimum power consumption.