Fully-Synthesizable Current-Input ADCs for Ultra-Low Area and Minimal Design Effort

A fully synthesizable ADC architecture is proposed for low-end current sensing applications. Being based on standard cells and designed with a fully-automated flow, the proposed ADC allows very low area, digital-like scaling across CMOS technology generations, technology and design portability, minimal design effort, and immersed-in logic design (i.e., low integration effort), compared to traditional analog-intensive designs. In addition, it allows direct current readout without requiring a transresistance stage. Testchip measurements show a 5-nA to 1-μ A input range, 6.7-bit ENOB and 2.2-kS/s sample rate, at 940-nW power and 4,580-μ m
²
area. To the best of the authors' knowledge, this testchip is the first demonstration of a fully-synthesizable input-current ADC. Along with the analysis of the specific limitations of the presented demonstration, this work aims to pave the way for a new class of current-input ADCs that can be designed and integrated with logic within hours, and occupy a silicon area in the order of 10kgates.