Event driven simulation without loops or conditionals

The past several years have seen much research in event driven logic simulation. Various logic and delay models have been explored. Most simulation research has focused on improving simulation performance. New approaches to both compiled and event driven simulation have been explored. The internal operations of event-driven simulators can be divided into two categories, scheduling, and gate simulation. Much effort has been focused on reducing the cost of scheduling. There has also been effort to reduce the cost of gate simulation. It has also been shown that explicit computation of gate outputs is unnecessary, as long as event propagation is computed correctly. Even though research has reduced the complexity of both scheduling and gate simulation, it is still necessary to test for event propagation and cancellation, and it is necessary to perform some computations during gate simulation. This paper shows that none of these computations are necessary. Most computations are devoted to testing internal states and computing new internal states. In our technique, subroutine addresses are used to maintain states. This permits the elimination of all state-testing and state-computation code. Our technique is significantly faster than conventional event-driven simulation. Unlike earlier methods, our approach can easily be extended to any logic model or any delay model.