System Level Design Verification Testing for Different Interconnected units with Hardware-in-the-loop (HIL) Simulation

In complex systems, testing each interface of a system separately is not a coherent way of testing and it reduces test quality. Especially in design verification tests, increasing test quality can be achieved by testing system level reactions and responses of all interfaces together simultaneously considering the system as a whole. In this study, a test system created for design verification tests of four different units through Hardware-in-theloop (HIL) simulation is to be explained. Design verification tests covering whole interfaces of Unit Under Test (UUT) are demonstrated with also simulations of units to be connected to UUT. The overall test system is divided into two main parts as automatic test equipment (ATE) design and HIL simulation design. The design process of ATE includes test requirements, specifications and identifications of all interfaces which belong to interconnected units in the system. The hardware selections and connections between them are accomplished for four different UUTs in such a manner that they can be tested together or separately. In the design process of HIL simulation, each sub-system connected to UUTs and UUTs themselves are considered separately. The requirements for each sub-system and each UUT are met within the interface control documents. In order to increase the quality of test, communications and the control of the electrical interfaces between each sub-system are implemented in real time. The communication interfaces consist of RS422, RS485, MILSTD-1553, Telnet and CANopen. The reactions and responses of each UUT are collected and HIL simulation is improved. Finally, the discussions about the approach of design verification tests of four different UUTs within HIL simulation and the improvement of the test quality are revealed. Further in this study, the test approach used by DEICO for HIL is discussed in detail.